Invention Grant
US07824982B2 DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DRAM arrays
有权
DRAM阵列,垂直晶体管结构以及形成晶体管结构和DRAM阵列的方法
- Patent Title: DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DRAM arrays
- Patent Title (中): DRAM阵列,垂直晶体管结构以及形成晶体管结构和DRAM阵列的方法
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Application No.: US11955251Application Date: 2007-12-12
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Publication No.: US07824982B2Publication Date: 2010-11-02
- Inventor: Leonard Forbes
- Applicant: Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John PS
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/04

Abstract:
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.
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