Invention Grant
- Patent Title: Methods of providing electrical isolation in semiconductor structures
- Patent Title (中): 在半导体结构中提供电隔离的方法
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Application No.: US12131608Application Date: 2008-06-02
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Publication No.: US07824983B2Publication Date: 2010-11-02
- Inventor: Werner Juengling
- Applicant: Werner Juengling
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/335

Abstract:
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.
Public/Granted literature
- US20090294840A1 METHODS OF PROVIDING ELECTRICAL ISOLATION AND SEMICONDUCTOR STRUCTURES INCLUDING SAME Public/Granted day:2009-12-03
Information query
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