Invention Grant
US07824984B2 Method of fabricating a trench DMOS (double diffused MOS) transistor
失效
制造沟槽DMOS(双扩散MOS)晶体管的方法
- Patent Title: Method of fabricating a trench DMOS (double diffused MOS) transistor
- Patent Title (中): 制造沟槽DMOS(双扩散MOS)晶体管的方法
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Application No.: US12244009Application Date: 2008-10-02
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Publication No.: US07824984B2Publication Date: 2010-11-02
- Inventor: Jeong Pyo Hong
- Applicant: Jeong Pyo Hong
- Applicant Address: KR Seoul
- Assignee: Dongbu Hitek Co., Ltd.
- Current Assignee: Dongbu Hitek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Saliwanchik, Lloyd & Saliwanchik
- Priority: KR10-2007-0136237 20071224
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Disclosed is a method of fabricating a semiconductor device. The method can include forming a gate material layer on an inner surface of a trench which extends into a part of a semiconductor substrate by passing through an insulating layer formed on the semiconductor substrate, etching the gate material layer to an initial height in the trench above a top surface of the semiconductor substrate, etching the insulating layer such that the thickness of the insulating layer is reduced, forming a gate electrode in the trench by secondarily etching the etched gate material layer, and removing the insulating layer having the reduced thickness.
Public/Granted literature
- US20090159989A1 Semiconductor Device and Method of Fabricating the Same Public/Granted day:2009-06-25
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