Invention Grant
- Patent Title: Method for reducing overlap capacitance in field effect transistors
- Patent Title (中): 降低场效应晶体管重叠电容的方法
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Application No.: US12050596Application Date: 2008-03-18
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Publication No.: US07824989B2Publication Date: 2010-11-02
- Inventor: Huilong Zhu , Oleg Gluschenkov
- Applicant: Huilong Zhu , Oleg Gluschenkov
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Daniel Schnurmann
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.
Public/Granted literature
- US20080166848A1 METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS Public/Granted day:2008-07-10
Information query
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