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US07824989B2 Method for reducing overlap capacitance in field effect transistors 有权
降低场效应晶体管重叠电容的方法

Method for reducing overlap capacitance in field effect transistors
Abstract:
A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.
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