Invention Grant
US07825003B2 Method of doping field-effect-transistors (FETs) with reduced stress/strain relaxation and resulting FET devices
有权
掺杂具有减小的应力/应变弛豫和所得FET器件的场效应晶体管（FET）的方法
- Patent Title: Method of doping field-effect-transistors (FETs) with reduced stress/strain relaxation and resulting FET devices
- Patent Title (中): 掺杂具有减小的应力/应变弛豫和所得FET器件的场效应晶体管（FET）的方法
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Application No.: US11768266Application Date: 2007-06-26
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Publication No.: US07825003B2Publication Date: 2010-11-02
- Inventor: Robert J. Gauthier, Jr. , Rajendran Krishnasamy
- Applicant: Robert J. Gauthier, Jr. , Rajendran Krishnasamy
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Edward W Brown
- Main IPC: H01L21/76
- IPC: H01L21/76
Abstract:
A method for fabricating a FET transistor for an integrated circuit by the steps of forming recesses in a substrate on both sides of a gate on the substrate, halo/extension ion implanting into the recesses, and filling the recesses with embedded strained layers comprising dopants for in-situ doping of the source and drain of the transistor. The stress/strain relaxation of the resulting transistor is reduced.
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Information query
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