Invention Grant
- Patent Title: Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits
- Patent Title (中): 减小半导体集成电路中寄生电容的结构和方法
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Application No.: US11863724Application Date: 2007-09-28
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Publication No.: US07825019B2Publication Date: 2010-11-02
- Inventor: Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Vidhya Ramachandran
- Applicant: Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin Shawn Petrarca , Vidhya Ramachandran
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Daniel Schnurmann
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.
Public/Granted literature
- US20090085210A1 STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS Public/Granted day:2009-04-02
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