Invention Grant
US07825022B2 Method of enabling solder deposition on a substrate and electronic package formed thereby
有权
能够在基板上形成焊料沉积的方法和由此形成的电子封装
- Patent Title: Method of enabling solder deposition on a substrate and electronic package formed thereby
- Patent Title (中): 能够在基板上形成焊料沉积的方法和由此形成的电子封装
-
Application No.: US12387417Application Date: 2009-04-30
-
Publication No.: US07825022B2Publication Date: 2010-11-02
- Inventor: Ravi Nalla , Charavana Gurumurthy
- Applicant: Ravi Nalla , Charavana Gurumurthy
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kenneth A. Nelson
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
Public/Granted literature
- US20090277866A1 Method of enabling solder deposition on a substrate and electronic package formed thereby Public/Granted day:2009-11-12
Information query
IPC分类:
