Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than that of the base portion. A memory element is on a top surface of the pillar portion of the bottom electrode, and a top electrode is on the memory element. A dielectric spacer contacts the outer surface of the pillar portion, the outer surface of the base portion of the bottom electrode self-aligned with an outer surface of the dielectric spacer.