Invention Grant
- Patent Title: Strained layers within semiconductor buffer structures
- Patent Title (中): 半导体缓冲结构内的应变层
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Application No.: US12562029Application Date: 2009-09-17
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Publication No.: US07825401B2Publication Date: 2010-11-02
- Inventor: Nyles W. Cody , Christophe Figuet , Mark Kennard
- Applicant: Nyles W. Cody , Christophe Figuet , Mark Kennard
- Applicant Address: US AZ Phoenix FR Crolles Cedex
- Assignee: ASM America, Inc.,S.O.I. Tec Silicon On Insulator Technologies, S.A.
- Current Assignee: ASM America, Inc.,S.O.I. Tec Silicon On Insulator Technologies, S.A.
- Current Assignee Address: US AZ Phoenix FR Crolles Cedex
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L29/06
- IPC: H01L29/06

Abstract:
A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate.
Public/Granted literature
- US20100006893A1 STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES Public/Granted day:2010-01-14
Information query
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