Invention Grant
US07825431B2 Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection
有权
降低了具有静电放电(ESD)电路保护功能MOSFET的掩模配置
- Patent Title: Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection
- Patent Title (中): 降低了具有静电放电(ESD)电路保护功能MOSFET的掩模配置
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Application No.: US12006398Application Date: 2007-12-31
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Publication No.: US07825431B2Publication Date: 2010-11-02
- Inventor: Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
- Applicant: Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
- Applicant Address: BM
- Assignee: Alpha & Omega Semicondictor, Ltd.
- Current Assignee: Alpha & Omega Semicondictor, Ltd.
- Current Assignee Address: BM
- Agent Bo-In Lin
- Main IPC: H01L29/72
- IPC: H01L29/72 ; H01L23/62

Abstract:
A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
Public/Granted literature
- US20090166740A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection Public/Granted day:2009-07-02
Information query
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