Invention Grant
- Patent Title: Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages
- Patent Title (中): 半导体封装,堆叠半导体封装以及制造半导体封装和堆叠半导体封装的方法
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Application No.: US12003544Application Date: 2007-12-28
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Publication No.: US07825468B2Publication Date: 2010-11-02
- Inventor: Yong-Chai Kwon , Dong-Ho Lee
- Applicant: Yong-Chai Kwon , Dong-Ho Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2006-0137859 20061229
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L23/04 ; H01L23/48

Abstract:
A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.
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