Invention Grant
- Patent Title: High bond line thickness for semiconductor devices
- Patent Title (中): 半导体器件的高键合线厚度
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Application No.: US11935915Application Date: 2007-11-06
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Publication No.: US07825501B2Publication Date: 2010-11-02
- Inventor: Zhengyu Zhu , Yi Li , FangFang Yang
- Applicant: Zhengyu Zhu , Yi Li , FangFang Yang
- Applicant Address: US DE
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US DE
- Agency: Kirton & McConkie
- Agent Kenneth E. Horton
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
Die attach methods used in making semiconductor devices and the semiconductor devices resulting from those methods are described. The methods include providing a leadframe with a die attach pad, using boundary features to define a perimeter on the die pad, depositing a conductive material (such as solder) within the perimeter, and then bonding a die containing an integrated circuit to the die pad by using the conductive material. The boundary features allow an increased thickness of conductive material to be used, resulting in an increased bond line thickness and increasing the durability and performance of the resulting semiconductor device.
Public/Granted literature
- US20090115039A1 High Bond Line Thickness For Semiconductor Devices Public/Granted day:2009-05-07
Information query
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