Invention Grant
US07825516B2 Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures 有权
在多层半导体结构中形成对准的封盖金属线和互连

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures
Abstract:
In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .
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