Invention Grant
- Patent Title: Minimizing power consumption of a reference voltage circuit using a capacitor
- Patent Title (中): 使用电容器降低参考电压电路的功耗
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Application No.: US12454721Application Date: 2009-05-21
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Publication No.: US07825639B1Publication Date: 2010-11-02
- Inventor: Hidehiko Suzuki , Hidenori Kobayashi , Nicky Miles Johnson
- Applicant: Hidehiko Suzuki , Hidenori Kobayashi , Nicky Miles Johnson
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01M10/46
- IPC: H01M10/46

Abstract:
A system and method is disclosed for minimizing power consumption in a reference voltage circuit. A capacitor is coupled to a reference voltage circuit and charged to a voltage that equals the reference voltage of the reference voltage circuit. The capacitor is then decoupled from the reference voltage circuit and power to the reference voltage circuit is turned off. The capacitor then provides the capacitor voltage to other circuits as a reference voltage. After a selected period of time has elapsed since the capacitor was last charged to the reference voltage, the reference voltage circuit is turned on and the capacitor is again coupled to the reference voltage circuit. The reference voltage circuit then recharges the capacitor to the reference voltage level. This process is repeated to periodically charge the capacitor to the reference voltage.
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