Invention Grant
- Patent Title: Test pad design for reducing the effect of contact resistances
- Patent Title (中): 测试垫设计，以减少接触电阻的影响
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Application No.: US12196531Application Date: 2008-08-22
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Publication No.: US07825678B2Publication Date: 2010-11-02
- Inventor: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
- Applicant: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G01R31/02
- IPC: G01R31/02
Abstract:
An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
Public/Granted literature
- US20100045325A1 Test Pad Design for Reducing the Effect of Contact Resistances Public/Granted day:2010-02-25
Information query
