A multiphase clock generation circuit (111) for generating a multiphase clock signal, a phase subdivision unit (113) for shifting a phase of the multiphase clock signal output from the multiphase clock generation circuit (111), and a clock selection unit (114) for selecting one of clock signals output from the phase subdivision unit (113) are provided. A PLL circuit (120) for receiving an output from a frequency division circuit (115) is further provided. The phase shift carried out by the phase subdivision unit (113) and the selection of the clock signal carried out by the clock selection unit (114) are controlled by a frequency control unit (112) to switch SSC ON/OFF and to change the bandwidth of the PLL circuit (120).