A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals.