Class D amplifier is resistant to interferences. Binary output signals y1 and y2, are generated from input signal s1, delivered to input terminal IN, to drive a load connected across output terminals OUTP and OUTN. Pulse generating circuit 10 generates a pulse width modulated pulse signal y0 from input signal s1, inverted signal of the output signal y1 and output signal y2. Differential pulse generating circuit 14 receives pulse signal y0 and inverts low and high levels of pulse signal y0, while shifting the resulting signal by half period from the pulse signal y0, to generate a pulse signal y3. Pulse amplifier 11a receives pulse signal y0 and generates output signal y1 supplied to output terminal OUTP. Pulse amplifier 11b receives pulse signal y3 and generates output signal y2 delivered to output terminal OUTN.