Invention Grant
- Patent Title: Apparatus for low-jitter frequency and phase locked loop and associated methods
- Patent Title (中): 低抖动频率和锁相环及相关方法的设备
-
Application No.: US12334701Application Date: 2008-12-15
-
Publication No.: US07825737B1Publication Date: 2010-11-02
- Inventor: Steve Fang , Chi Fung Cheng
- Applicant: Steve Fang , Chi Fung Cheng
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: H03L7/087
- IPC: H03L7/087
Abstract:
A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.
Information query
IPC分类:
