Invention Grant
US07825777B1 Packet processors having comparators therein that determine non-strict inequalities between applied operands
有权
其中具有比较器的分组处理器确定应用操作数之间的非严格不等式
- Patent Title: Packet processors having comparators therein that determine non-strict inequalities between applied operands
- Patent Title (中): 其中具有比较器的分组处理器确定应用操作数之间的非严格不等式
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Application No.: US11393489Application Date: 2006-03-30
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Publication No.: US07825777B1Publication Date: 2010-11-02
- Inventor: Tingjun Wen , David Walter Carr , Tadeusz Kwasniewski
- Applicant: Tingjun Wen , David Walter Carr , Tadeusz Kwasniewski
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, Inc.
- Current Assignee: Integrated Device Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Myers, Bigel, et al.
- Main IPC: G05B1/00
- IPC: G05B1/00 ; H03K19/20 ; H03K19/094 ; G06F7/00
Abstract:
An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ( ( C i ( A 0 + B 0 _ ) + A 0 B 0 _ ) ( A 1 + B 1 _ ) + A 1 B 1 _ ) … ( A n - 2 + B n - 2 _ ) + A n - 2 B n - 2 _ ) ( A n - 1 + B n - 1 _ ) + A n - 1 B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.
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