A pre-processor pre-processes enhanced data packets by coding the enhanced data packets for forward error correction (FEC) and expanding the FEC-coded data packets. A data formatter adds first null data into first place holders within each pre-processed enhanced data packet. A first multiplexer multiplexes the main data packets with the enhanced data packets having the first null data. A holder inserter inserts second null data into second place holders within an enhanced data packet outputted from the first multiplexer. A data interleaver replaces the second null data with parity data. A data generator generates at least one known data sequence. A symbol processor replaces the first null data included in an output of the data interleaver with the known data sequence(s). A non-systematic RS encoder generates the parity data by performing non-systematic RS-coding on an output of the symbol processor, and provides the parity data to the data interleaver.