A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit (230) for outputting a second pre-decoded address (PDA2) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer (240) for selecting either the first or second pre-decoded address (PDA1 or PDA2) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.