Invention Grant
- Patent Title: Non-volatile memory cell read failure reduction
- Patent Title (中): 非易失性存储单元读取故障降低
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Application No.: US12566202Application Date: 2009-09-24
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Publication No.: US07826274B2Publication Date: 2010-11-02
- Inventor: Seiichi Aritome
- Applicant: Seiichi Aritome
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G11C16/06
- IPC: G11C16/06

Abstract:
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations.
Public/Granted literature
- US20100014352A1 NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION Public/Granted day:2010-01-21
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