A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF2 makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND2 makes the DQS signal maskable with a mask signal MS.