A semiconductor memory device includes: a driving voltage supplying unit configured to detect a simultaneous activation of banks and selectively supply one of a high voltage and an external voltage lower than the high voltage as a driving voltage; a flag detecting unit configured to detect inputs of flag signals activated in response to an active command and generate a precharge control signal; and a signal generating unit configured to generate a bit line precharge signal swinging between the driving voltage and a ground voltage in response to the precharge control signal.