A network-on-chip apparatus including a plurality of network interfaces being independently connected to a plurality of processing elements; a network including a plurality of switches for controlling data transmission/reception between the network interfaces; and a plurality of bidirectional links for connecting between the network interfaces and the switches, and between the switches. The network interface includes an output packet buffer for outputting sequentially stored packets to a corresponding switch via the link connected to an output packet port; an input packet buffer for sequentially storing a packet received from the switch via an input packet port; a packet composer and decomposer for composing a packet using an address signal, a control signal and a data signal received from the processing elements, storing the composed packet in the output packet buffer, decomposing a packet provided from the input packet buffer, decrypting the decomposed packet, and delivering the decrypted packet to the processing elements; and an autonomic clock control unit for controlling a clock frequency being output to the corresponding processing element according to a backlog of the output packet buffer.