Invention Grant
US07826497B2 Data receiving circuit that can correctly receive data, even when high-speed data transmission is performed, using small amplitude clock
有权
数据接收电路即使在执行高速数据传输时也能正确接收数据，使用小振幅时钟
- Patent Title: Data receiving circuit that can correctly receive data, even when high-speed data transmission is performed, using small amplitude clock
- Patent Title (中): 数据接收电路即使在执行高速数据传输时也能正确接收数据，使用小振幅时钟
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Application No.: US10328031Application Date: 2002-12-26
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Publication No.: US07826497B2Publication Date: 2010-11-02
- Inventor: Yoshiyasu Doi , Hirotaka Tamura
- Applicant: Yoshiyasu Doi , Hirotaka Tamura
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Arent Fox LLP
- Priority: JP2002-149119 20020523
- Main IPC: H04J3/04
- IPC: H04J3/04 ; H03H11/26
Abstract:
A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.
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