Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die.