Invention Grant
US07827355B1 Data processor having a cache with efficient storage of predecode information, cache, and method
有权
数据处理器具有具有高效存储预解码信息，高速缓存和方法的高速缓存
- Patent Title: Data processor having a cache with efficient storage of predecode information, cache, and method
- Patent Title (中): 数据处理器具有具有高效存储预解码信息，高速缓存和方法的高速缓存
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Application No.: US10887069Application Date: 2004-07-08
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Publication No.: US07827355B1Publication Date: 2010-11-02
- Inventor: Karthikeyan Muthusamy , Brian D. McMinn
- Applicant: Karthikeyan Muthusamy , Brian D. McMinn
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries Inc.
- Current Assignee: GlobalFoundries Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F15/00 ; G06F7/38 ; G06F9/00 ; G06F9/44
Abstract:
A data processor (200) includes an instruction cache (220) and a secondary cache (250). The instruction cache (220) has a plurality of cache lines. Each of the plurality of cache lines stores a first plurality of bits (222) corresponding to at least one instruction and a second plurality of bits (224, 226) associated with the execution of the at least one instruction. The secondary cache (250) is coupled to the instruction cache (220) and stores cache lines from the instruction cache (250) by storing the first plurality of bits (222) and a third plurality of bits (255, 257) corresponding to the second plurality of bits (224, 226). The third plurality of bits (255, 257) is fewer in number than the second plurality of bits (224, 226).
Information query
