A processing device comprises a processor, low power nonvolatile memory that communicates with the processor, high power nonvolatile memory that communicates with the processor. The processing device manages data using a cache hierarchy comprising a high power (HP) nonvolatile memory level for data in the high power nonvolatile memory and a low power (LP) nonvolatile memory level for data in the low power nonvolatile memory. The LP nonvolatile memory level has a higher level in the cache hierarchy than the HP nonvolatile memory level.