A fault tolerant computer comprises a first unit, a second unit, a delay buffer and a delay time setting unit. The first unit executes a computer program in response to an input signal. The second unit executes the computer program in the same execution environment as the first unit in response to the input signal. The delay buffer controls a delay time of a timing when the input signal is input to the first unit with respect to a timing when the input signal is input to the second unit. The delay time setting unit sets the delay time to zero when receiving a synchronization mode signal and sets the delay time to be larger than zero when receiving a delay mode signal.