Invention Grant
- Patent Title: Error catch RAM support using fan-out/fan-in matrix
- Patent Title (中): 使用扇出/扇入矩阵捕获RAM支持错误
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Application No.: US11895512Application Date: 2007-08-24
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Publication No.: US07827452B2Publication Date: 2010-11-02
- Inventor: Edmundo De La Puente
- Applicant: Edmundo De La Puente
- Applicant Address: SG Singapore
- Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Holland & Hart, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.
Public/Granted literature
- US20090055690A1 Error catch RAM support using fan-out/fan-in matrix Public/Granted day:2009-02-26
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