Invention Grant
- Patent Title: Low-density parity-check decoder apparatus
- Patent Title (中): 低密度奇偶校验解码装置
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Application No.: US11857305Application Date: 2007-09-18
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Publication No.: US07827461B1Publication Date: 2010-11-02
- Inventor: Seo-How Low , Nedeljko Varnica , Gregory Burd , Zining Wu
- Applicant: Seo-How Low , Nedeljko Varnica , Gregory Burd , Zining Wu
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A low-density parity-check (LDPC) decoder includes a plurality of bit node processing elements, and a plurality of check node processing elements. The LDPC decoder also includes a plurality of message passing memory blocks. A first routing matrix couples the plurality of bit node processing elements to the plurality of message passing memory blocks. A second routing matrix couples the plurality of check node processing elements to the plurality of message passing memory blocks. The first routing matrix and the second routing matrix enable each bit node to exchange LDPC decoding messages with an appropriate check node via a corresponding one of the message passing memory blocks.
Information query
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