发明授权
US07830017B2 Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package
有权
晶圆级芯片尺寸封装,其制造方法,以及包括晶圆级芯片级封装的半导体芯片模块
- 专利标题: Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package
- 专利标题(中): 晶圆级芯片尺寸封装,其制造方法,以及包括晶圆级芯片级封装的半导体芯片模块
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申请号: US11950251申请日: 2007-12-04
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公开(公告)号: US07830017B2公开(公告)日: 2010-11-09
- 发明人: In-Young Lee , Dong-Ho Lee , Nam-Seog Kim , Hyun-Soo Chung , Ho-Jin Lee , Myeong-Soo Park
- 申请人: In-Young Lee , Dong-Ho Lee , Nam-Seog Kim , Hyun-Soo Chung , Ho-Jin Lee , Myeong-Soo Park
- 申请人地址: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- 代理机构: Muir Patent Consulting, PLLC
- 优先权: KR10-2006-0122587 20061205
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L23/52
摘要:
Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.