Invention Grant
US07830017B2 Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package
有权
晶圆级芯片尺寸封装,其制造方法,以及包括晶圆级芯片级封装的半导体芯片模块
- Patent Title: Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package
- Patent Title (中): 晶圆级芯片尺寸封装,其制造方法,以及包括晶圆级芯片级封装的半导体芯片模块
-
Application No.: US11950251Application Date: 2007-12-04
-
Publication No.: US07830017B2Publication Date: 2010-11-09
- Inventor: In-Young Lee , Dong-Ho Lee , Nam-Seog Kim , Hyun-Soo Chung , Ho-Jin Lee , Myeong-Soo Park
- Applicant: In-Young Lee , Dong-Ho Lee , Nam-Seog Kim , Hyun-Soo Chung , Ho-Jin Lee , Myeong-Soo Park
- Applicant Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2006-0122587 20061205
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52

Abstract:
Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.
Public/Granted literature
Information query
IPC分类: