A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line.