Invention Grant
- Patent Title: Method of fabricating quad flat non-leaded package
- Patent Title (中): 制造四方扁平无铅封装的方法
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Application No.: US12332362Application Date: 2008-12-11
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Publication No.: US07842550B2Publication Date: 2010-11-30
- Inventor: Chun-Ying Lin , Geng-Shin Shen , Po-Kai Hou
- Applicant: Chun-Ying Lin , Geng-Shin Shen , Po-Kai Hou
- Applicant Address: TW Hsinchu
- Assignee: ChipMOS Technologies Inc.
- Current Assignee: ChipMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW97143129A 20081107
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.
Public/Granted literature
- US20100120201A1 METHOD OF FABRICATING QUAD FLAT NON-LEADED PACKAGE Public/Granted day:2010-05-13
Information query
IPC分类: