Invention Grant
- Patent Title: Chip package, chip packaging, chip carrier and process thereof
- Patent Title (中): 芯片封装，芯片封装，芯片载体及其工艺
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Application No.: US11162898Application Date: 2005-09-27
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Publication No.: US07842597B2Publication Date: 2010-11-30
- Inventor: Yu-Pin Tsai
- Applicant: Yu-Pin Tsai
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Jianq Chyun IP Office
- Priority: TW93132321A 20041026
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.
Public/Granted literature
- US20060088955A1 CHIP PACKAGE, CHIP PACKAGING, CHIP CARRIER AND PROCESS THEREOF Public/Granted day:2006-04-27
Information query
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