Invention Grant
- Patent Title: Interconnecting board and three-dimensional wiring structure using it
- Patent Title (中): 互连板和三维接线结构使用它
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Application No.: US11995339Application Date: 2006-04-17
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Publication No.: US07845954B2Publication Date: 2010-12-07
- Inventor: Yoshihiro Tomura , Yasushi Nakagiri , Kunio Hibino , Yoshihiko Yagi , Akihiro Miyashita , Masahiro Ono , Masato Mori
- Applicant: Yoshihiro Tomura , Yasushi Nakagiri , Kunio Hibino , Yoshihiko Yagi , Akihiro Miyashita , Masahiro Ono , Masato Mori
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Steptoe & Johnson LLC
- Priority: JP2005-205012 20050714
- International Application: PCT/JP2006/308062 WO 20060417
- International Announcement: WO2007/007450 WO 20070118
- Main IPC: H01R12/00
- IPC: H01R12/00

Abstract:
A first circuit board (1) mounted with an electronic component (16) and a second circuit board (2) are vertically connected three-dimensionally through an interconnecting board (3) wherein the terminal portion (6) of the land electrode (5) on the interconnecting board (3) is buried in the termination material (9) of the interconnecting board (3). Consequently, the chance of peeling or cracking due to peeling stress or shearing stress acting between the upper/lower circuit boards and the land electrode by high density mounting, thermal shock or falling impact can be suppressed or buffered resulting in high reliability.
Public/Granted literature
- US20080139013A1 Interconnecting Board and Three-Dimensional Wiring Structure Using it Public/Granted day:2008-06-12
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