Invention Grant
- Patent Title: Wafer level package and method of fabricating the same
- Patent Title (中): 晶圆级封装及其制造方法
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Application No.: US12498913Application Date: 2009-07-07
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Publication No.: US07847416B2Publication Date: 2010-12-07
- Inventor: Hyun-Soo Chung , In-Young Lee , Son-Kwan Hwang , Dong-Ho Lee , Seong-Deok Hwang
- Applicant: Hyun-Soo Chung , In-Young Lee , Son-Kwan Hwang , Dong-Ho Lee , Seong-Deok Hwang
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Myers Bigel Sibley & Sajovec, PA
- Priority: KR2006-45802 20060522
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.
Public/Granted literature
- US20090267211A1 WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2009-10-29
Information query
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