A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.