发明授权
- 专利标题: Low cost bumping and bonding method for stacked die
- 专利标题(中): 堆叠模具的低成本碰撞和接合方法
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申请号: US12242492申请日: 2008-09-30
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公开(公告)号: US07863092B1公开(公告)日: 2011-01-04
- 发明人: Raghunandan Chaware , Arifur Rahman
- 申请人: Raghunandan Chaware , Arifur Rahman
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理商 Michael R. Hardaway; Thomas George; LeRoy D. Maunu
- 主分类号: H01L21/44
- IPC分类号: H01L21/44 ; H01L21/48 ; H01L21/50
摘要:
Disclosed is a method of fabricating an integrated circuit assembly in which a plurality of mother dice having a plurality of through-die vias (TDVs) are formed in the first (active) surface of a semiconductor wafer, a substrate is attached to the active surface of the wafer, the second (inactive) surface is back-ground to expose one end of the through-die vias, a plurality of daughter dice are mounted to the inactive surface of the wafer, each daughter die being electrically coupled to a mother die, and the mother dice are then singulated. Attaching the substrate can be accomplished by adhering a glass wafer carrier to the wafer. The wafer carrier allows handling of the wafer during back-grinding the inactive surface, forming under-bump metal (UBM) pads on the TDVs and attaching the daughter dice.
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IPC分类: