Invention Grant
- Patent Title: Signal delay structure in high speed bit stream demultiplexer
- Patent Title (中): 高速位流解复用器中的信号延迟结构
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Application No.: US12613740Application Date: 2009-11-06
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Publication No.: US07864909B2Publication Date: 2011-01-04
- Inventor: Jun Cao , Guangming Yin
- Applicant: Jun Cao , Guangming Yin
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Garlick Harrison & Markison
- Agent Shayne X. Short; Bruce E. Garlick
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.
Public/Granted literature
- US20100054384A1 SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER Public/Granted day:2010-03-04
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