发明授权
US07865850B1 Method and apparatus for substrate noise aware floor planning for integrated circuit design
有权
用于集成电路设计的基板噪声感知楼层规划的方法和装置
- 专利标题： Method and apparatus for substrate noise aware floor planning for integrated circuit design
- 专利标题（中）： 用于集成电路设计的基板噪声感知楼层规划的方法和装置
-
申请号： US12037843申请日： 2008-02-26
-
公开(公告)号： US07865850B1公开(公告)日： 2011-01-04
- 发明人: William Kao , Xiaopeng Dong
- 申请人： William Kao , Xiaopeng Dong
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Schwegman, Lundberg & Woessner, P.A.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A methodology is provided to perform noise analysis in the implementation stage of the design of an integrated circuit, and based upon analysis results, a floorplan may be adjusted or guard rings may be inserted to reduce the impact of digital switching noise upon noise sensitive circuits.
信息查询
