Invention Grant
- Patent Title: Method for fabricating buried capacitor structure
- Patent Title (中): 掩埋电容器结构的制造方法
-
Application No.: US12479811Application Date: 2009-06-07
-
Publication No.: US07871892B2Publication Date: 2011-01-18
- Inventor: Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen , Yu-Te Lu
- Applicant: Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen , Yu-Te Lu
- Applicant Address: TW Taoyuan
- Assignee: Kinsus Interconnect Technology Corp.
- Current Assignee: Kinsus Interconnect Technology Corp.
- Current Assignee Address: TW Taoyuan
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.
Public/Granted literature
- US20100307666A1 Method For Fabricating Buried Capacitor Structure Public/Granted day:2010-12-09
Information query
IPC分类: