发明授权
- 专利标题: Method of design analysis of existing integrated circuits
- 专利标题(中): 现有集成电路设计分析方法
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申请号: US12200975申请日: 2008-08-29
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公开(公告)号: US07873203B2公开(公告)日: 2011-01-18
- 发明人: Vyacheslav L. Zavadsky , Val Gont , Edward Keyes , Jason Abt , Stephen Begg
- 申请人: Vyacheslav L. Zavadsky , Val Gont , Edward Keyes , Jason Abt , Stephen Begg
- 申请人地址: CA
- 专利权人: Semiconductor Insights Inc.
- 当前专利权人: Semiconductor Insights Inc.
- 当前专利权人地址: CA
- 代理机构: Price, Reneveld, Cooper, DeWitt & Litton, LLP
- 主分类号: G06K9/00
- IPC分类号: G06K9/00
摘要:
The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
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