A bit-level turbo code encoder is provided. The bit-level turbo code encoder is configured to receive a first input data sequence and generate a first output data sequence. The bit-level turbo code encoder includes a first non-binary convolutional code encoder, a bit-level interleaver, and a second non-binary convolutional code encoder. The first non-binary convolutional code encoder is configured to process the first input data sequence and generate a second output data sequence. The bit-level interleaver is configured to receive the first input data sequence as a first sequence and interleave the first sequence at bit level to generate a fourth sequence. The second non-binary convolutional code encoder is coupled with the bit-level interleaver and configured to receive the fourth sequence and process the fourth sequence to generate a third output data sequence.