Invention Grant
US07877713B2 Method and apparatus for substrate noise analysis using substrate tile model and tile grid
有权
使用基板瓦片模型和瓦片网格进行基板噪声分析的方法和装置
- Patent Title: Method and apparatus for substrate noise analysis using substrate tile model and tile grid
- Patent Title (中): 使用基板瓦片模型和瓦片网格进行基板噪声分析的方法和装置
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Application No.: US11769670Application Date: 2007-06-27
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Publication No.: US07877713B2Publication Date: 2011-01-25
- Inventor: Vinod Kariat , Xiaopeng Dong , David Noice
- Applicant: Vinod Kariat , Xiaopeng Dong , David Noice
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance.
Public/Granted literature
- US20090007032A1 METHOD AND APPARATUS FOR SUBSTRATE NOISE ANALYSIS USING SUBSTRATE TILE MODEL AND TILE GRID Public/Granted day:2009-01-01
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