A display with a display unit is configured so that pixels are arrayed in a matrix. A clock pulse generating means generates clock pulses of any frequency. Based on the generated clock pulses, a pulse generating means generates timing signals for parallel arrangement processing video signals in units of a plurality of pixels as pulse signals enabling free setting of a pulse width and a pulse period. A phase deviation detecting means detects the amounts of phase deviation after write signals generated based on the timing signals and for writing video signals into the plurality of pixels pass through the display unit. The timing adjusting means automatically performs adjustment so that the amount of phase deviation is within the predetermined range (so that it becomes almost zero) based on the amounts of phase deviation detected by the phase deviation detecting means.