A method for reducing dark current within a charge-coupled device, the method includes each gate phase n having a capacitance Cn, voltage change on the gate phase n given by ΔVn such ∑ n ⁢ C n ⁢ Δ ⁢ ⁢ V n ≅ 0 ; for the first time period, maintaining a set of first gate phases holding charge in the accumulated state and maintaining a set of second gate phases not holding charge in the depleted state; for a second time period, clocking the charge into a set of third gate phases in the depleted state and clocking the second set of gate phases not holding charge into the accumulated state; for a third time period, clocking the third set of gate phases holding the charge into the accumulated state and clocking a fourth set of gates not holding the charge into the depletion state; wherein the second time period is shorter than the first and third time periods.