Invention Grant
US07881111B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells
有权
具有电可擦除和可编程的半导体存储器单元的半导体存储器
- Patent Title: Semiconductor memory having electrically erasable and programmable semiconductor memory cells
- Patent Title (中): 具有电可擦除和可编程的半导体存储器单元的半导体存储器
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Application No.: US12504307Application Date: 2009-07-16
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Publication No.: US07881111B2Publication Date: 2011-02-01
- Inventor: Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
- Applicant: Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corporation
- Current Assignee: Renesas Technology Corporation
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP1997-139019 19970528
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
Public/Granted literature
- US20100014351A1 SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS Public/Granted day:2010-01-21
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